搜索资源列表
irq_cpu
- This file define the irq handler for MIPS CPU interrupts.
cpu
- MIPS流水线CPU的工作原理和设计方法-The design and implementation of the pipelined CPU
3-David_Harris-Mpis-cpu
- mips的源码 基于hmtl的 学习计算机组成原理的同学可以-mips source hmtl based learning computer organization students can look
See_MIPS_Run-2nd
- MIPS架构CPU的入门书籍，此书讲述了在通用MIPS CPU 上编程需要了解的一切知识。-Book for beginner of CPU of MIPS Architecture，it tells all the knowledge need for the development on the MIPS CPU.
cpu
- MIPS指令CPU模拟器-MIPS instruction CPU simulator ............................................. ......
MIPS-and-CPU-design-and-simulation
- 兼容MIPS指令集的CPU设计与仿真 处理器架构为多周期，指令用32为字长（取指占一个周期），4k的存储器（指令存储器和数据存储器分开），IO与存储器统一编制，能支持20条指令以上-MIPS instruction set compatible CPU design and simulation
Lab7
- CSCE2214课程设计，试验7源代码。实现单周期的MIPS CPU 16位。-CSCE2214 curriculum design, test 7 source code. Achieve single-cycle MIPS CPU 16 place.
Lab9-Forwarding-Unit
- CSCE2214课程设计，试验9源代码。实现流水线结构的MIPS CPU 16位。配有强大的Forwarding Unit.-CSCE2214 curriculum design, test 9 source code. Implement pipelined MIPS CPU 16 place. With a strong Forwarding Unit.
fs2_ex
- 用于mips系统开发，能够进行调试，开发，跟踪。开发mips系统的启动。-for mips cpu development
m3u8streamtv_2.9_all
- Python开发的扩展件，用于基于MIPS Cpu 的Enigma2固件下流媒体播放。所有采用MIPs处理器的机顶盒都可以安装。-m3u8 extension for Enigma 2
micro-op_cpu
- MIPS 微程序多周期cpu，mips的部分代码实现-MIPS cpu micro-program multi-cycle
multi-CPU
- 多时钟CPU设计，spartan 3e板上试验通过，支持部分mips指令，内含示例mips代码及二进制文件-Multiple CPU clock design, spartan 3e board test passed, support some mips instruction, containing sample code and binary files mips
single-CPU
- 单时钟CPU设计，spartan 3e板上试验通过，支持部分mips指令，内含示例mips代码及二进制文件-Single CPU clock design, spartan 3e board test passed, support some mips instruction, containing sample code and binary files mips
simple-pipeLine-CPU
- 简单的流水线CPU实现，基于MIPS指令集。-Simple pipelined CPU implementation, based on the MIPS instruction set.
scmips_cpu
- 自己写的单周期mips CPU和测试工程-Write your own single cycle mips CPU and test engineering
cpu
- 用vhdl实现了具有流水的cpu，实现30条基于mips指令的指令集-Achieved with vhdl cpu with water, to achieve 30 mips instruction based instruction set
多周期cpu
- 多周期cpu,11条mips指令集，仅供参考
pipeline_mipscpu
- 运用Verilog语言实现MIPS五级CPU的功能，能下载实现-5-level MIPS CPU based on Verilog
cpu_design
- FPGA MIPS架构CPU，五段流水线功能，ISE开发，verilog语言，可综合，模拟结果正确，内含设计报告-FPGA MIPS CPU, simple five-stage pipeline function, developed by ISE, using verilog language
cpu
- Suspend support specific for mips.